UVM (Universal Verification Methodology)
An Verification Methodology (UVM) to verify the hardware, most popular in
industry, more efficient and powerful way compared to System-Verilog, provides a
lot flexibility for reusability of the environment, it is a factory-based mechanism,
provides a lot of inbuilt methods.
Project
- Verification of a design(Flop,FIFO,LIFO,RAM)
- VIP/UVC development of a protocol(SPI, AMBA)
Course Material
- Soft copy of session notes with block diagrams
- 24x7 doubts clearance
- Assignments
- Interview Level Questions
- Live quiz for skill enhancementt
- Mock Interview & Written Test
Universal Verification Methodology
An Verification Methodology (UVM) to verify the hardware, most popular in
industry, more efficient and powerful way compared to System-Verilog, provides a
lot flexibility for reusability of the environment, it is a factory-based mechanism,
provides a lot of inbuilt methods.
Basic test bench structure
Test bench hierarchy
UVM phases
Implementation of UVM objects and components
Calling of inbuilt Methods
Factory Overriding
Stimulus generation
Driver, Sequencer handshaking mechanism
Sequence, Sequencer communication
Config_db vs Resource_db
Sequence, Sequencer communication
Printing mechanism
Severity and Verbosity levels
TLM connections
UVM (Universal Verification Methodology)
An Verification Methodology (UVM) to verify the hardware, most popular in
industry, more efficient and powerful way compared to System-Verilog, provides a
lot flexibility for reusability of the environment, it is a factory-based mechanism,
provides a lot of inbuilt methods.