System-Verilog
An Hardware Verification Language used to verify the functionality of Design
which is coded in Verilog/VHDL language to ensure that circuit is bug free and
working as per the user requirement.
System-Verilog
Basic testbench structure
System Verilog data types VS Verilog Data types
OOPs
– class
– Inheritance
– Polymorphism
– Encapsulation
– Abstract class
– Casting
– Copy mechanism
– Scope resolution operator
– Extern declaration
Arrays and Queues and their methods
Operators
Constraints
Randomization
Semaphore
Events
Threads
Mailbox mechanism
Program block
System-Verilog Loops
System-Verilog Task and Functions
Functional Coverage
Projects
- Verification of an Design (Flop,FIFO,LIFO,RAM)
- VIP development of a protocol(SPI,AMBA)
Course Material
- Soft copy of session notes with block diagrams
- E-Books
- 24x7 doubts clearance
- Assignments
- Mock Interview & Written Test
- Interview questions
- Live quiz for skill enhancement
System-Verilog
An Hardware Verification Language used to verify the functionality of Design
which is coded in Verilog/VHDL language,to ensure that circuit is bug free and
working as per the user requirement.