eMicrobyte - Complete Functional Verification Training

Complete Functional Verification Training

It is a complete Verification Program, espically designed for the freshers, includes ADD, Verilog, System-Verilog, UVM and projects, it intension behind the training program is to target the freshers and get ready for the job.

Advance Digital Design Overview

Advance digital design(ADD) is the basic requirement to lean VLSI, it is used to design an Digital circuit as per customer requirement It is 4 weekend training program.

Basics of Analog Electronics

Number System

Combinational Circuits
– Basic gates
– Multiplexer/De-multiplexer
– Adders/Subtractors
– Encoder/Decoder
– Implementation of Digital circuits using Multiplexers

Sequential Circuits

– Difference between Combinational and Sequential circuits
– Concept behind clock and Reset
– Active low resets
– Latches
– Flip-Flops
– Counters

Finite State Machine

– Melay Machine
– Moore Machine
– Difference Between Melay and Moore Machin

Course Material

Project

Course Material

Soft copy of session notes with block diagrams
24x7 doubts clearance
Assignments
Interview Level Questions
Live quiz for skill enhancementt
Mock Interview & Written Test

Verilog HDL

Verilog is a Hardware Description Language, used to develop a code for a Hardware as per the application requirement

Basics of Verilog

Compiler directive and system tasks

Data types

Module and Ports

Gate level Modelling
-Implementation of gates
-Designing of basic combination and sequential circuits

Data Flow Modelling
-Operators
-Blocking assignments
-Continuous assignment and their rules
-Implementation of various kind of circuits using Continuous assignment

Behavioural Modelling
-Procedural assignment
-Non-blocking assignments
-Sensitivity list
-Synchronous and Asynchronous modelling
-Verilog loops
-If-else ladder
-Case statement
-Task and Functions
-Procedural and Continuous assignment
-Named block

Mixed Modelling approach
-Designing of Digital circuits using Data Flow and Behavioural modelling together

Testbench Development
-Signal declaration
-Port connection
-Clock and Reset generation
-Test vector generation
-Initial and Final Blocks

System-Verilog

An Hardware Verification Language, used to verify the functionality of Design which is coded in Verilog/VHDL language,to ensure that circuit is bug free and working as per the user requirement

Basic testbench structure

System Verilog data types VS Verilog Data types

OOPs
– class
– Inheritance
– Polymorphism
– Encapsulation
– Abstract class
– Casting
– Copy mechanism
– Scope resolution operator
– Extern declaration

Arrays and Queues and their methods

Operators

Constraints

Randomization

Semaphore

Events

Threads

Mailbox mechanism

Program block

System-Verilog Loops

System-Verilog Task and Functions

Functional Coverage

Projects

Course Material

Soft copy of session notes with block diagrams
E-Books
24x7 doubts clearance
Assignments
Mock Interview & Written Test
Interview questions
Live quiz for skill enhancement

Project

Course Material

Soft copy of session notes with block diagrams
24x7 doubts clearance
Assignments
Interview Level Questions
Live quiz for skill enhancementt
Mock Interview & Written Test

Universal Verification Methodology

An Verification Methodology (UVM) to verify the hardware, most popular in industry, more efficient and powerful way compared to System-Verilog, provides a lot flexibility for reusability of the environment, it is a factory-based mechanism, provides a lot of inbuilt methods.

Basic test bench structure

Test bench hierarchy

UVM phases

Implementation of UVM objects and components

Calling of inbuilt Methods

Factory Overriding

Stimulus generation

Driver, Sequencer handshaking mechanism

Sequence, Sequencer communication

Config_db vs Resource_db

Sequence, Sequencer communication

Printing mechanism

Severity and Verbosity levels

TLM connections