Verilog HDL
Verilog is a Hardware Description Language, used to develop a code for a
Hardware as per the application requirement.
Project
- Designing of single port RAM
- Designing of dual port RAM
- Designing of FIFO/LIFO
- Designing of AMBA/SPI protocol slave
Course Material
- Soft copy of session notes with block diagrams
- 24x7 doubts clearance
- Assignments
- Interview Level Questions
- Live quiz for skill enhancementt
- Mock Interview & Written Test
Verilog HDL
Basics of Verilog
Compiler directive and system tasks
Data types
Module and Ports
Gate level Modelling
-Implementation of gates
-Designing of basic combination and sequential circuits
Data Flow Modelling
-Operators
-Blocking assignments
-Continuous assignment and their rules
-Implementation of various kind of circuits using Continuous assignment
Behavioural Modelling
-Procedural assignment
-Non-blocking assignments
-Sensitivity list
-Synchronous and Asynchronous modelling
-Verilog loops
-If-else ladder
-Case statement
-Task and Functions
-Procedural and Continuous assignment
-Named block
Mixed Modelling approach
-Designing of Digital circuits using Data Flow and Behavioural modelling together
Testbench Development
-Signal declaration
-Port connection
-Clock and Reset generation
-Test vector generation
-Initial and Final Blocks
Verilog HDL
Verilog is a Hardware Description Language, used to develop a code for a
Hardware as per the application requirement.